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--- sd-8516_programmer_s_reference_guide [2026/01/29 18:45] – appledog
+++ sd-8516_programmer_s_reference_guide [2026/01/30 02:03] (current) – appledog
@@ Line 4: / Line 4: @@
 The **Stellar Dynamics SD-8516** represents a categoretroical reimagining of microprocessor architecture. This 16-bit CPU, implemented in AssemblyScript for the VC-3 computer system, delivers performance exceeding conventional silicon constraints through advanced cross-boundary resonance microcascades.
-**Key Specifications:**
+The SD-8516 is intended to be an easy to learn architecture which remains era-authentic.
+^ CPU ^ Opcodes ^ Assembler ^ Notes ^
+|
+| SD-8516 | 56 opcodes | 105 opcodes | |
+| 6809 | 59 opcodes | 154+ | "the most elegant 8 bit CPU ever designed" |
+| 8086 | 117 opcodes | 117 | standard of the era |
+| 6502 | 151 opcodes | 151 | standard of the era |
+| Z80 | 158 opcodes | hundreds | prefix machine--158 base opcodes |
+| 8080 | 244 opcodes | | |
+=== Key Specifications
 * 16-bit architecture with 16 general-purpose registers
 * 32-bit and 64-bit register pairing system
@@ Line 11: / Line 23: @@
 * ~20× performance improvement over legacy 8510 design
-== Performance Characteristics ==
+=== Measured Performance:
-**Measured Performance:**
 * Clock speed: 10 MHz base, up to 100 MHz
 * Sustained MIPS: 70 MIPS (i7-12700k)
@@ Line 18: / Line 29: @@
 * Sound system overhead: < 5% CPU time
 * Video refresh: 60 Hz (16.67ms frame time)
-**Optimization Notes:**
-* Batch instruction execution (787,401 instructions per batch at 100 MIPS target)
-* MessageChannel-based scheduling for low-latency loops
-* Time-debt throttling maintains consistent clock rate
-* Sound updates triggered by register writes (not polling)
 == Technical Implementation
-**Architecture:** WebAssembly-based virtual CPU
+* **Architecture:** WebAssembly-based virtual CPU
-**Languages:** AssemblyScript (CPU core), JavaScript (I/O systems)
+* **Languages:** AssemblyScript (CPU core), JavaScript (I/O systems)
-**Memory Model:** 4 banks of 64k RAM
+* **Memory Model:** 4 banks of 64k RAM
-**Audio Backend:** SD-450 4 voice polyphonic 5 waveform Audio System
+* **Audio Backend:** SD-450 4 voice polyphonic 5 waveform Audio System
-**Video Backend:** 9 mode Text and Graphics pixel-perfect render engine
+* **Video Backend:** 9 mode Text and Graphics pixel-perfect render engine
+== Lore
+Since the days of the first minicomputers, Stellar Dynamics has been at the forefront of microarchitecture design. The SD-8516 is not simply an iteration upon its predecessors; it is a categorical reimagining of what a "processor" can be when unshackled from quantum locality.
+While our earliest designs struggled with resonance cascade instability, the SD-8516 delivers stable, predictable cross-boundary resonance microcascades at clock rates exceeding the theoretical limits of conventional silicon.
+These advancements position the Stellar Dynamics SD-8516 as the definitive architecture for next-generation computation: a bridge between classical logic engines and the emergent technologies of multidimensional processing.
 <blockquote>This SD-8516 PROGRAMMER'S REFERENCE GUIDE has been developed as a working tool and reference source for those of you who want to maximize your use of the built-in capabilities of your VC-3 Computer System. This manual contains the information you need for your programs, from the simplest example all the way to the most complex. The PROGRAMMER'S REFERENCE GUIDE is designed so that everyone from the beginning BASIC programmer to the professional experienced in SD-8516 machine language can get information to develop his or her own creative programs. At the same time this book shows you how clever your SD-8516 really is.
@@ Line 53: / Line 64: @@
 Think of your SD-8516 PROGRAMMER'S REFERENCE GUIDE as a useful tool to help you and you will enjoy the hours of programming ahead of you.</blockquote>
-== System Lore
-Since the days of the first minicomputers, Stellar Dynamics has been at the forefront of microarchitecture design. The SD-8516 is not simply an iteration upon its predecessors; it is a categorical reimagining of what a "processor" can be when unshackled from quantum locality.
-While our earliest designs struggled with resonance cascade instability, the SD-8516 delivers stable, predictable cross-boundary resonance microcascades at clock rates exceeding the theoretical limits of conventional silicon.
-These advancements position the Stellar Dynamics SD-8516 as the definitive architecture for next-generation computation: a bridge between classical logic engines and the emergent technologies of multidimensional processing.
 == CPU Architecture
@@ Line 83: / Line 88: @@
 | R15 | Z | General Purpose |
-**Note:** The SD-8516 does not use register pairing except for multiplication operations, which store results in the AB register pair.
+== Register Encoding
+=== Byte Access
+Each register's high and low bytes are individually addressable using H/L suffixes: AH/AL, BH/BL, XH/XL, etc.
+=== 32-bit Pairs
+Adjacent registers can be combined for certain 32-bit operations using concatenated names:
+- AB = A (high) + B (low)
+- CD = C (high) + D (low)
+- EF, GI, JK, LM, TY, XZ
+This is simulated 32 bit access; changing the value of a 32 bit pair will corrupt the underlying 16 bit registers, and so forth. Secondly, access is only marginally faster than 16 bit access; for memory loads, stores and compares it is usually faster to use native 16-bit mode.
+=== 24-bit Pointers
+Memory addressing uses a bank byte plus 16-bit offset. The naming convention is `[low-byte][offset]`:
+- BLX = BL (bank) + X (address)
+- ELM = EL (bank) + M (address)
+- FLD = FL (bank) + D (address)
+- GLK = GL (bank) + K (address)
-=== Register Encoding
+Eight bank registers (BL, EL, FL, GL, IL, JL, LL, TL) each pair with eight address registers (A, C, D, K, M, X, Y, Z), yielding 64 possible 24-bit pointer combinations.
-Registers are encoded as 4-bit values (0-15), allowing two registers per byte:
-* Low nibble: First operand
-* High nibble: Second operand
-Example: {{{ADD A, B}}} encodes as {{{0x01}}} (A=0, B=1)
+=== Register Overlap
+As with their 32-bit counterparts, 24-bit pointers share components. ELM and ELD both use the EL bank byte. FLD and GLD both use the D address register. Modifying one affects the other -- a common source of bugs. Always verify pointer independence when using multiple pointers simultaneously.
 === Flags Register
@@ Line 331: / Line 351: @@
 | SEV | Set overflow flag |
 | CLV | Clear overflow flag |
+=== Other
+|= Instruction |= Description |
+| TSX | Transfer SP to register* |
+| TXS | Transfer register to SP* |
+* (*) these opcodes were suggested by stackminer from the Fantasy Console 2.0 discord. Thank you, stackminer!
 === System Operations
@@ Line 475: / Line 503: @@
 ---
-**SD-8516 Technical Manual** - Revision 1.0
+**SD-8516 Technical Manual** - Revision 1.0\\
-**Copyright © 2025 Appledog Hu**
+**Copyright © 2025 Appledog Hu**\\
 **All specifications subject to change as quantum resonance research continues.**