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--- sd-8516_programmer_s_reference_guide [2026/01/29 18:50] – appledog
+++ sd-8516_programmer_s_reference_guide [2026/01/30 02:03] (current) – appledog
@@ Line 3: / Line 3: @@
 == Introduction
 The **Stellar Dynamics SD-8516** represents a categoretroical reimagining of microprocessor architecture. This 16-bit CPU, implemented in AssemblyScript for the VC-3 computer system, delivers performance exceeding conventional silicon constraints through advanced cross-boundary resonance microcascades.
+The SD-8516 is intended to be an easy to learn architecture which remains era-authentic.
+^ CPU ^ Opcodes ^ Assembler ^ Notes ^
+|
+| SD-8516 | 56 opcodes | 105 opcodes | |
+| 6809 | 59 opcodes | 154+ | "the most elegant 8 bit CPU ever designed" |
+| 8086 | 117 opcodes | 117 | standard of the era |
+| 6502 | 151 opcodes | 151 | standard of the era |
+| Z80 | 158 opcodes | hundreds | prefix machine--158 base opcodes |
+| 8080 | 244 opcodes | | |
 === Key Specifications
@@ Line 76: / Line 88: @@
 | R15 | Z | General Purpose |
-**Note:** The SD-8516 does not use register pairing except for multiplication operations, which store results in the AB register pair.
+== Register Encoding
+=== Byte Access
+Each register's high and low bytes are individually addressable using H/L suffixes: AH/AL, BH/BL, XH/XL, etc.
-=== Register Encoding
+=== 32-bit Pairs
-Registers are encoded as 4-bit values (0-15), allowing two registers per byte:
+Adjacent registers can be combined for certain 32-bit operations using concatenated names:
-* Low nibble: First operand
+- AB = A (high) + B (low)
-* High nibble: Second operand
+- CD = C (high) + D (low)
+- EF, GI, JK, LM, TY, XZ
-Example: {{{ADD A, B}}} encodes as {{{0x01}}} (A=0, B=1)
+This is simulated 32 bit access; changing the value of a 32 bit pair will corrupt the underlying 16 bit registers, and so forth. Secondly, access is only marginally faster than 16 bit access; for memory loads, stores and compares it is usually faster to use native 16-bit mode.
+=== 24-bit Pointers
+Memory addressing uses a bank byte plus 16-bit offset. The naming convention is `[low-byte][offset]`:
+- BLX = BL (bank) + X (address)
+- ELM = EL (bank) + M (address)
+- FLD = FL (bank) + D (address)
+- GLK = GL (bank) + K (address)
+Eight bank registers (BL, EL, FL, GL, IL, JL, LL, TL) each pair with eight address registers (A, C, D, K, M, X, Y, Z), yielding 64 possible 24-bit pointer combinations.
+=== Register Overlap
+As with their 32-bit counterparts, 24-bit pointers share components. ELM and ELD both use the EL bank byte. FLD and GLD both use the D address register. Modifying one affects the other -- a common source of bugs. Always verify pointer independence when using multiple pointers simultaneously.
 === Flags Register
@@ Line 324: / Line 351: @@
 | SEV | Set overflow flag |
 | CLV | Clear overflow flag |
+=== Other
+|= Instruction |= Description |
+| TSX | Transfer SP to register* |
+| TXS | Transfer register to SP* |
+* (*) these opcodes were suggested by stackminer from the Fantasy Console 2.0 discord. Thank you, stackminer!
 === System Operations
@@ Line 468: / Line 503: @@
 ---
-**SD-8516 Technical Manual** - Revision 1.0
+**SD-8516 Technical Manual** - Revision 1.0\\
-**Copyright © 2025 Appledog Hu**
+**Copyright © 2025 Appledog Hu**\\
 **All specifications subject to change as quantum resonance research continues.**